Recent Developments

Two-stage execute pipeline (up from one)

Fits better with 2-stage load/store pipeline

Allows 32-bit multiplies to execute without stalling the pipeline

Bypass paths implemented from both stages back to decode2

Integer division and 64-bit multiplications done by FPU (if present)

Division uses reciprocal estimation, Newton-Raphson refinement, multiply, adjust

Simple Branch Target Cache in fetch1

Stores instruction address and target address for direct branch instructions

Enables zero-overhead loops provided loop body is >= 3 instructions long

Moved instruction address translation from icache to fetch1

2-entry “ERAT” plus iTLB in fetch1

Icache now accessed using real addresses => set size no longer constrained to 4kB

Instruction pre-decoding before icache

Compute a 10-bit instruction index from instruction word

Index replaces major opcode in icache => 36 bits per instruction in icache

 (index for illegal instructions is 0x200 + major opcode)

Instruction indexes assigned in groups so range tests can be used

e.g., does it have RB operand? does it access FPRs vs GPRs?

Implemented (most) SFFS instructions added in v3.1

br[hwd], cnt[lt]zdm, set[n]bc[r]

Prefixed instructions

Prefixed load/store instructions, paddi, pnop, etc. (SFFS subset)

Added support for vestigial 1-entry “partition table” to MMU

Process table base address read from (PTCR + 8)

Added basic PMU (Performance Monitor Unit)

Implements architected events and a few others

Doesn’t implement random sampling

Added snooping logic to dcache and icache

Added micro-SD card interface using Litex “litesdcard” logic

Added GPIO (general-purpose I/O) interface

Access RAM arrays synchronously wherever possible

Enables use of block RAM in FPGA implementations

GPR/FPR register file requires addresses to be supplied from decode1 rather than decode2; addresses generated from instruction index and instruction word in parallel with decode table lookup

Many performance/timing improvements and logic simplifications

Testing

1000 randomly-generated code sequences with results from POWER9

Results compared via a checksum of integer register contents

Doesn’t include floating-point or privileged instructions

simple_random program to generate pseudo-random instruction sequences

Can run on two machines and compare results

Unit test programs

Generally these try executing specific instructions on specific operands, or exercise specific system functionality

branch_alias, decrementer, fpu, illegal, misc, mmu, modes, pmu, prefix, privileged, reservation, sc, spr_read, trace, xics

Boot Linux and observe behavior

Floating-point test suites, benchmarks, etc. can be run under Linux

Experiments

Implemented lq, stq, lqarx, stqcx.

Required “instruction doubling” to handle 128 bits

Atomicity requirements hard to implement (but also hard to observe)

Partial VMX/VSX implementation

Also used instruction doubling

Implemented instructions used in glibc compiled for POWER9

Cache coherency for multi-core implementation

Including correct behavior for larx/stcx, sync, dcbf, etc.

Hardware random number generator

Micro-programmed control for FPU (in development)

Memory management unit – implementation

Add level-1 TLBs to instruction and data caches

4kB page size, looked up in parallel with cache tags

Instruction TLB is direct-mapped, 64 entries

Data TLB is 2-way set associative, 128 entries total

MMU is a state machine

Sends a series of requests to the dcache to read the process table and PTEs

Eventually sends the translation to the dcache or icache

EA bits inserted if page size > 4kB

Currently no caching of PTEs or PDEs in the MMU

Nor any caching of partial translation results (no “page walk cache”)

Just the L1 iTLB and dTLB inside the instruction and data caches

Microwatt doesn’t implement the partition table

Instead has a PRTBL register (SPR) to point to the process table

Floating-point unit

Why do a FPU?

It’s in the architecture

Don’t want to define a soft-float ABI – want to avoid fragmentation

How small can we make it?

What are the difficulties?

Divide and square-root instructions

Fused multiply-add instructions

Handling denormalized numbers and exception conditions correctly

Getting correct results down to the last bit in all rounding modes

Results:

Control uses a state machine: handle one instruction at a time, not pipelined

Uses about 4500 LUTs on the Xilinx Artix-7 (~20% of the total SoC)

Add/subtract generally take 5–12 cycles, multiply takes 8–15 cycles