https://sites.google.com/site/kochiuyu/Tikz  draw  Ref  Latex 

TLV  ( VLSI tool )

IoT Edge  Design  and Making   

 1)  TL-Verilog constructs  into SystemVerilog 

    http://www.redwoodeda.com/products SandPiper™

2) SystemVerilog into   C++

https://www.veripool.org  Verilator 

3)  Navigation 

  http://www.graphviz.org    graphviz

4) Editor   

https://codemirror.net/ CodeMirror

5) Packaging 

  System on package (SOP) 

Package on package (POP) 

Wire bond package  

Flip-chip package 

6)  Design to Device  

Verilog-to-FPGA compilers  

Verilog to generate geometric structures of transistors

Verilog simulators (which compile it to native machine code or to the C

Verilog [Compiler] 

Gate level Netlist 

 [Place & Route tool]  GDS2