Working with GHDL
sudo apt update
sudo apt install snapd
sudo snap install ghdl
Example https://github.com/JulyWitch/vhdl_ghdl_examples
git clone https://github.com/JulyWitch/vhdl_ghdl_examples.git
cd vhdl_ghdl_examples
make I=<input_file> T=<test_bench_file> E=<test_bench_entity_name>
make I=test/counter.vhdl T=test/counter.test.vhdl E=counter_tb
.... output ...
ghdl -a -fsynopsys --std=08 test/counter.vhdl test/counter.test.vhdl
ghdl -e -fsynopsys --std=08 counter_tb
ghdl -r -fsynopsys --std=08 counter_tb --vcd=waves/counter_tb.vcd --wave=waves/counter_tb.ghw --stop-time=1us
/snap/ghdl/1/bin/ghdl:info: simulation stopped by --stop-time @1us
..............
This will generate wave and vcd files to the waves directory.
Then open generated .ghw or .vcd file with gtkwave.
make I=test/counter.vhdl T=test/counter.test.vhdl E=counter_tb S_TIME=1ms
https://github.com/JulyWitch/vhdl_ghdl_examples/tree/master/test
Example Using GHDL and GTKWave
Compile VHD File and Generate Object File, to see the output, you need to run the simulation. Here are the steps:
Open Your VHDL Simulation Tool: Use a VHDL simulation tool like ModelSim, Vivado, or GHDL.
Compile the Design and Testbench: Compile both the xor_gate and xor_gate_tb files.
# Compile the design and testbench
ghdl -a xor_gate.vhdl
ghdl -a xor_gate_tb.vhdl
# Elaborate the testbench
ghdl -e xor_gate_tb
Simulation of Design
Run the Simulation:
Run the simulation for xor_gate_tb. The simulator will show the waveform and you can observe the values of signals a, b, and y.
# Run the simulation and generate a waveform file
ghdl -r xor_gate_tb --vcd=waveform.vcd
# View the waveform using GTKWave
gtkwave waveform.vcd
Microwatt: Emulation in FPGA
his Makefile is set up for a hardware design project using GHDL, Yosys, and Verilator. Below is an explanation of the key components:
GHDL ?= ghdl : Sets the GHDL variable to ghdl if not already defined.
GHDLFLAGS=--std=0: Specifies that the VHDL standard to be used is 2008.
CFLAGS=-O3 -Wall Sets the compiler flags to optimize the code (-O3) and enable all warning messages Wall
VERILATOR_FLAGS=-O3 -Wno-fatal -Wno-CASEOVERLAP -Wno-UNOPTFLAT}: Specifies the flags for Verilator, disabling certain warnings.
ifeq (\$(VERILATOR_TRACE),1)}: If \texttt{VERILATOR\_TRACE is set to 1, additional flags for tracing are added.
GHDLSYNTH ?= \$(shell (\$(YOSYS) -H | grep -q ghdl) || echo -m ghdl): Checks if Yosys has the GHDL plugin built in, otherwise adds the \texttt{-m ghdl} flag.
YOSYS, NEXTPNR, ECPPACK, ECPPROG, OPENOCD, VUNITRUN, VERILATOR, DFUUTIL, DFUSUFFIX: These variables are set to their respective tool names or commands.
DOCKER ?= 0, PODMAN ?= 0: These variables determine whether Docker or Podman is used.
ifeq (\$(DOCKER), 1): If Docker is enabled, it sets up the Docker command and arguments.
ifeq (\$(USE\_DOCKER), 1): If Docker or Podman is used, it configures the necessary commands for running tools inside containers.
PWD = \$(shell pwd): Gets the current working directory.
DOCKERARGS = run --rm -v \$(PWD: /src:z -w /src}: Sets the arguments for Docker.
all = core\_tb icache_tb dcache_tb dmi\_dtm_tb wishbone_bram_tb soc_reset_tb: Lists all the testbenches to be built.
core\_files, soc\_files, uart_files, soc\_sim\_files, soc\_sim\_c\_files: These variables contain lists of VHDL source files.
sim\_dram\_c.o, soc_dram\_sim\_obj\_files, soc\_dram\_sim\_link: Variables related to the simulation of DRAM using Verilator.
microwatt.json, microwatt.v, microwatt-verilator}: Targets for synthesizing and building the Microwatt core using Yosys and Verilator.
prog, microwatt.svf, microwatt.dfu: Targets for programming the FPGA.
tests, check, check_light: Targets for running different sets of tests.
clean, distclean: Targets for cleaning up build artifacts.
Makefile also includes configurations for different FPGA targets like ECPIX-5, OrangeCrab, and ECP5-EVN. Each target has specific settings for clock frequencies, constraints, and packages.
jk@jkhome:~/dev/VHDL/microwatt/microwatt$ make
cc -O3 -Wall -c -o sim_vhpi_c.o sim_vhpi_c.c
cc -O3 -Wall -c -o sim_bram_helpers_c.o sim_bram_helpers_c.c
cc -O3 -Wall -c -o sim_console_c.o sim_console_c.c
cc -O3 -Wall -c -o sim_jtag_socket_c.o sim_jtag_socket_c.c
ghdl -i --std=08 --work=unisim --workdir=sim-unisim sim-unisim/BSCANE2.vhdl sim-unisim/BUFG.vhdl sim-unisim/unisim_vcomponents.vhdl
ghdl -c --std=08 -Psim-unisim -Wl,sim_vhpi_c.o -Wl,sim_bram_helpers_c.o -Wl,sim_console_c.o -Wl,sim_jtag_socket_c.o decode_types.vhdl common.vhdl wishbone_types.vhdl fetch1.vhdl utils.vhdl plrufn.vhdl cache_ram.vhdl icache.vhdl predecode.vhdl decode1.vhdl helpers.vhdl insn_helpers.vhdl control.vhdl decode2.vhdl register_file.vhdl cr_file.vhdl crhelpers.vhdl ppc_fx_insns.vhdl rotator.vhdl logical.vhdl countbits.vhdl multiply.vhdl multiply-32s.vhdl divider.vhdl execute1.vhdl loadstore1.vhdl mmu.vhdl dcache.vhdl writeback.vhdl core_debug.vhdl core.vhdl fpu.vhdl pmu.vhdl wishbone_arbiter.vhdl wishbone_bram_wrapper.vhdl sync_fifo.vhdl wishbone_debug_master.vhdl xics.vhdl syscon.vhdl gpio.vhdl soc.vhdl spi_rxtx.vhdl spi_flash_ctrl.vhdl git.vhdl sim_console.vhdl sim_pp_uart.vhdl sim_bram_helpers.vhdl sim_bram.vhdl sim_jtag_socket.vhdl sim_jtag.vhdl dmi_dtm_xilinx.vhdl sim_16550_uart.vhdl foreign_random.vhdl glibc_random.vhdl glibc_random_helpers.vhdl core_tb.vhdl -e core_tb
/snap/ghdl/1/bin/ghdl:error: unknown warning identifier: l,sim_vhpi_c.o
make: *** [Makefile:128: core_tb] Error 1
jk@jkhome:~/dev/VHDL/microwatt/microwatt$